---------------------------------------------------------------------------- The Florida SunFlash The SuperSPARC Microprocessor Fact Sheet 4/92 SunFLASH Vol 41 #10 May 1992 ---------------------------------------------------------------------------- TEXAS INSTRUMENTS SUPERSPARC (TM) TMS390Z50 MICROPROCESSOR Key Features Integrated on Chip O SPARC Compatible - Runs old SPARC binaries and binaries compiles for SuperSPARC pipeline - Industry's only openly evolved architecture - Multiprocessing memory model (total store ordering and partial store ordering) O Flexible Superscalar Engine: Integer Unit Control, Superscalar Integer Execution - Executes up to three instructions per clock cycle - Abundant execution units for flexible scheduling of instructions - Fixed pipeline: Instructions move in groups through the pipeline - Unique arrangement of cascaded 32-bit ALUs (arithmetic logic units) for executing multiple integer instructions in the same clock - SPARC compatibility - dynamically groups and schedules instructions in hardware without the help of compilers. - Four instruction per cycle fetch, eight instruction prefetch queue, four instruction branch target queue - Low branch latency, handles most taken and untaken branches without pipeline stalls. - Single cycle, 64-bit loads and stores with no load-use penalty O High performance per MHz - 50 MHz cycle time scalable to 100 MHz over time - Four-way multiprocessing with a peak instruction execution of 600 million operations per second (MIPS) scalable to 1200 MIPs over time - Uniprocessing with a peak instruction execution of 150 MIPS scalable to 300 MIPS over time O High-Performance SPARC Floating-Point Unit - Complete single- and double-precision IEEE floating-point math - No unfinished operations - Tightly linked to integer pipeline, excellent performance balance - Integer multiply and divide O Largest On-Chip Caches of any RISC Microprocessor - Faster execution of real-world application software - 20-Kbyte instruction cache: 128-bit wide access, 5-way set associative, physically addressed, 32-byte sub-block, 64-byte lines, burst fill prefetch - 16-Kbyte data cache: 64-bit wide access, 4-way set associative, physically addressed, 32-byte sub-block, write back (no external cache), write through (external cache) O SPARC Reference MMU (memory management unit) - 64 entry, fully associative TLB - Hardware reload O Complete multiprocessing on-chip - MBus (multiprocessing bus) Level II fully synchronous chip- to-chip multiprocessor bus, coherent protocol, 64-bit wide datapath, snoop logic - Store/copyback buffer O SuperSPARC bus to external bus/cache controller (deselected if MBus mode) O System Support Features - Data and instruction prefetch for improved cache performance - Support for partial store ordering - Instruction or cycle counter - Phase locked loop for clock skew control O Extensive test/debug support - Built-in-self test - JTAG scan-based emulation - ICE-like debugging features O Packaging - High performance dense CPGA (ceramic pin grid array) with heatsink O Physical Characteristics - 3.1 million transistors - TI's 0.8 micron EPIC IIB triple metal BiCMOS process - Dense CMOS core with bipolar I/O and interconnect - Die size: 15.98 mm x 15.98 mm - Power supply: 5V +/- 5% - Power dissipation: 8 watts typical Companion SuperSPARC MultiCache Controller O Supports high performance uni- and multiprocessor systems - Cache tags and cache control for 1-MByte of external cache (MBus) or 512-KByte, 1-MByte or 2- MByte (XBus) - Built-in support for multiprocessing cache coherence - Highest SuperSPARC performance O Selectable System Bus Interface - Direct connect to industry-standard MBus - Packet interface supports other multiprocessing buses O Separate Bus and Processor Clocks - Processor may be operated at higher clock rates than the system bus - Allows simple performance upgrades O Test and Debug support - Built-in self test - JTAG (IEEE 1149.1) boundary scan and test O Other System Features - Efficient memory block copy and block initialize functions utilize system bus block transfers - 8-bit local peripheral bus (XBus only) - Data prefetching - Event counters allow cache performance to be monitored O Same EPIC IIB BiCMOS process as the SuperSPARC Microprocessor O 369 pin CPGA package ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ For information send mail to info-sunflash@sunvice.East.Sun.COM. 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