Intel Corporation Product Brief i750. video processor Overview Intels i750. video processor consists of two highly integrated VLSI components for implementing high-performance/low-cost DVI. multimedia video subsystems. The i750 video processor creates highly dynamic video displays featuring full-screen, full-motion video, video stills, video special effects, fast graphics and text. The pixel processor (82750PB) is a programmable video rate DSP that supports a wide range of compression and other videographics algorithms via an on-chip microcode instruction RAM. The programmable display processor (82750DB) reads bit maps from video RAM, provides final decompression of YUV (video format) bit maps and, for lowest system cost, includes an on-chip color look-up table and triple 8-bit DAC. Both chips contain software controlled special purpose hardware to accelerate frequently used videographics operations, such as filtering and statistical decoding. The i750 video processor is especially well suited to providing full multimedia and image processing capability in personal computer, workstation, and imbedded applications. Examples include point of sale terminals, ATMs, home players, information kiosks, video arcade games and medical imaging. Each component is packaged in a low-cost 132-pin plastic quad flat pack (PQFP) package and implemented in Intels 1.0 micron, high-speed CHMOS* IV technology. 82750PB Pixel Processor Product Highlights -25 MHz clock -Single-cycle instruction execution -512 x 48-bit microcode instruction RAM -Special video instructions -Pixel interpolator -2 input and 2 output 32-bit FIFO channels -Statistical decoder -50 MB/s maximum data rate -High-speed CHMOS IV technology -Low-cost 132-pin PQFP package Product Description The 82750PB is a 25MHz programmable video rate DSP that supports a wide range of videographics algorithms via an on-chip 512 x 48-bit microcode instruction RAM. When paired with its companion component, the 82750DB, the 82750PB creates highly dynamic video displays featuring full-screen, full motion video, video stills, video special effects, fast graphics and text. Single-cycle execution of all instructions plus on-chip instruction and data RAMs provide high pixel processing performance. The wide-word instruction format pushes performance higher by supporting multiple operations per instruction. The Arithmatic Logic Unit (ALU) has special video instructions, such as dual-add with saturate. Videographics performance is enhanced further by the addition of several software-controlled hardware accelerators. The pixel interpolator generates a weighted average of four pixels at the rate of one interpolated pixel per two clock cycles. This operation is used in the inner loops of many advanced video compression algorithms. Each 32-bit input/output FIFO channel has dedicated address generation, arbitration and data buffers. The hardware statistical decoder is a specialized input channel that decodes compressed bit stream data. 82750DB Display Processor Product Highlights - 28 MHz clock (VGA, NTSC) - 45 MHz clock (SVGA, PAL, XGA) - Programmable timing and sync, gen-lockable to external video - Programmable horizontal and vertical resolution. - Hardware line doubling (for motion video in a non-interlaced display) - Programmable pixel depth (8, 16, 32) - Two dimensional UV (chroma components) interpolator - Triple 256 x 8-bit color look-up table. - 16 x 16 x 2-bit hardware cursor - 2:1 Y horizontal interpolator - YUV to RGB conversion matrix - Auxiliary 8-bit alpha channel output - Triple 8-bit DAC - High-speed CHMOS IV technology - Low-cost 132-pin PQFP package Product Description The 82750DB is a high performance display processor which post-processes and displays videographics bit maps that have been created by its companion chip, the 82750PB. Video sync signals can be programmed to be compatible with all the popular sync standards (VGA, NTSC, PAL, XGA, SVGA) and the chip can be gen-locked to external video. The 82750DB features a large selection of bits/pixel, pixels/line and lines/screen (including hardware line doubling for motion video in a non-interlaced display), all definable via internal control registers. A two-dimensional interpolator provides real-time expansion of reduced sample density video chroma components (U, V) up to full resolution. The 2:1 Y horizontal interpolator can be used to smooth lower resolution video images. An on-chip transformation matrix converts digital YUV video components to digital RGB components. Low system cost is achieved by incorporating a triple 256 x 8-bit color look-up table and a triple 8-bit DAC on-chip. The RGB data is also available as a 24-bit digital output, accompanied by an 8-bit alpha channel output. *CHMOS is a patented process of Intel Corporation. Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. Intel retains the right to make changes to these specifications at any time, without notice. Contact your local sales office to obtain the latest specifications before placing your order. DVI and i750 are registered trademarks of Intel Corporation. ActionMedia is a trademark of Intel Corporation. CHMOS and HMOS are patented processes of Intel Corp. Printed copies of this manual or other Intel literature may be obtained from: Intel Corporation Literature Sales P.O. Box 7641 Mt. Prospect, IL 60056-764 1-800-548-4725 )1991 Intel Corporation Order Number 240868-003